1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a NAND flash memory in which each of memory cell transistors has a stacked gate structure constituted of a floating gate and control gate, and which includes an array of NAND memory cells each formed by connecting a pair of selection gate transistors in series to a plurality of memory cell transistors, and a stacked gate structure of a dummy NAND cell.
2. Description of the Related Art
In the cell array area of a NAND flash memory, a plurality of NAND memory cells (hereinafter referred to as NAND cells) is arranged in a matrix form. In each of the NAND cells, a plurality of non-volatile memory cell transistors is connected in series, and a selection gate transistor is connected to each of both ends of the plurality of memory cell transistors connected in series. Between NAND cells adjacent to each other in the row direction, an element isolation/insulation area (hereinafter referred to as an STI area) of a trench structure is formed. Each of the memory cell transistors has a stacked gate structure in which control gates are stacked on a floating gate via inter-gate insulating films (hereinafter referred to as IPD films) interposed between layers.
In Arai et al. (US2007/0138575), the following is described. That is, in a selection gate transistor, a lower gate electrode (in the same layer as the floating gate) and upper gate electrode (in the same layer as the control gate) are electrically connected to each other through an inter-gate connection trench opened in the IPD film.
Further, in MIYAZAKI et al. (US2008/03031115), the following is described. An STI area with a large width is formed on the substrate surface at an end part of a cell array area of a NAND flash memory in the row direction. A dummy element area, and a plurality of element areas are arranged in sequence adjacent to the STI area, and an STI area with a small width is arranged between the dummy element area and element area, and between element areas.
Further, in Shimizu et al. (U.S. Pat. No. 6,555,427), the following is described. In order to enhance the coupling ratio of the floating gate to control gate of a memory cell transistor, after formation of the STI area, the top surface of the insulating film of the STI area is recessed by isotropic or anisotropic etching, and the side surface of the floating gate is exposed. Areas other than the cell array area need not be etched, and hence are covered with a photoresist coating at the time of this process. The boundary of the photoresist coating is arranged in the dummy element area adjacent to the cell array side of the STI area with a large width. At the time of formation of the STI area, a pad nitride film is deposited on the element area. The pad nitride film and the surface of the insulating film of the STI area are planarized. Thereafter, the pad nitride film is removed. As a result of this, even after the above etching process, the STI area with the large width protrudes from the substrate surface of the adjacent dummy element area. The inter-gate connection trench opened in the IPD film between the upper gate electrode and lower gate electrode of the selection gate transistor is extended to a position of the dummy element area adjacent to the STI area with the large width.
When the cell array area of the NAND flash memory described above is formed, if the conventional mask layout is used, at a part in the STI area with the large width positioned at an end of the cell array area in the row direction, an etching remnant of the polysilicon film for the floating gate occurs in some cases in the column direction along the protrusion side surface of the step part protruding from the substrate surface. As a result of this, a short-circuit path for electrically connecting floating gates adjacent to each other in the column direction occurs along the STI area with the large width. Then, when a voltage is applied to a selection gate line connected to the selection gate transistor, the voltage is conducted to each floating gate of the memory cell transistors through the short-circuit path. As a result of this, a problem is caused as follows. That is, a high electric field is applied to the IPD film of the memory cell transistor, a breakdown of the IPD film occurs, further the high electric field is applied to the gate insulating film, and a breakdown of the gate insulating film is caused. Improvement of such a situation is desired.